Communication systems may be generally characterized as having two or more devices which communicate via an interconnect. In all communication systems, the transmission of data must be in some expected manner or order to maintain a meaning between the transmitting and receiving devices. The interconnects may be generally classified as being ordered or unordered. An unordered interconnect is an interconnect wherein information after being transmitted through the interconnect requires reordering at the destination. For example, in systems with unordered interconnects the output data from a transmitting device will not necessarily be received at a receiving device in the same data order that it was sent. For any one of a number of possible reasons, the interconnect may allow subsequently issued data to be passed forward of the earlier sent data. In such systems, a reordering process must be implemented at the destination of the data transmission. Disadvantages associated with systems having unordered interconnects include the expense associated with required hardware at destination points to perform the reordering function. Another disadvantage with systems having unordered interconnects is that such systems may require end-to-end retries to conform to proper ordering of data. Sometimes this reordering function may be implemented in software. An endpoint in an unordered system may encounter numerous concurrent requests from different sources. As a result, system performance quickly degrades due to the unpredictability of what order numerous data from potentially differing sources will be provided to a destination by the interconnect. Such systems may also require resource allocation which involves additional overhead and potential system performance degradation. Examples of types of systems having unordered interconnects include ethernet systems (IEEE 802), SCI systems (Scalable Coherent Interconnect, the IEEE 1596-1994 standard), ATM (Asynchronous Transfer Mode) systems and numerous other protocols commonly implemented for internet systems.
As an alternative to unordered interconnects, systems having ordered interconnects may be used. Examples of this type of system include PCI (Peripheral Component Interconnect) and PCI-X (Peripheral Component Interconnect Extensions). These protocols are very common for desktop computing systems. In these known systems with ordered interconnects, only one outstanding transaction is permitted to exist in the system between two devices. In other words, an acknowledge signal must be provided by a target device on the bus segment in which the transaction was initiated and received by the transmitting device before the transmitting device can provide a new transaction. That rule ensures certainty at a destination point that a transmitted transaction is received before another transaction is issued. This rule guarantees simplicity in the system and avoids any need for transaction reordering circuitry and resource allocation. However, because of the ensured certainty obtained by having only one outstanding transaction at any point in time in the interconnect, the system performance is reduced because of a lower amount of data being transmitted at the same time, especially for end-to-end transactions where the end devices are physically separated by a significant distance. Additionally, PCI and PCI-X require a synchronous system in which a transmitting endpoint device is clocked synchronously with a receiving endpoint device. The lower performance can be compensated for by using a higher clock frequency to clock the data, but clock rates are limited in speed due to the synchronous nature of the system. Even at higher clock speeds system performance is restrained by the single transaction nature of the interconnect. Synchronously clocked systems also require overhead to implement and maintain synchronous clocks at all endpoints of the system. Further limiting the performance of PCI and similar protocols is the fact that a transaction type is associated with each piece of data sent. In addition to creating such transaction types, both the interconnect and a receiving endpoint must then evaluate the type of data transaction and group similar type transactions together. All of these functions at numerous points in a system operate to add significant overhead to the system.
Data recovery to identify and correct data transmission errors is also a task which is not efficiently performed in many existing communication systems. For example, in ethernet-based systems, when more data packets exist in the interconnect than can be handled, the system is designed to drop or discard the data packets. The destination unit must then be configured to recognize that some data was not properly received and enter into an error recovery mode. Various known error recognition and error correction techniques exist. In most systems, error recovery is performed strictly in software. However, interrupting a device in the system to perform error recovery in software is slow. Additionally, many error recognition and recovery mechanisms will require additional end-to-end transfers within the system which is directly time dependent on the amount of distance separating the two endpoints. In some applications, the performance impact when requiring a software layer in the system for error recovery is unacceptable. Therefore, a need exists in known communication systems for improved efficiencies in the amount of overhead required to implement data transmissions and provide data error recovery.